Light-emitting diode chip package

ABSTRACT

A light-emitting diode chip package is provided. The light-emitting diode chip package includes a substrate; a light-emitting diode chip set (LED chip set) disposed over the substrate, wherein the LED chip set is formed by a plurality of light-emitting diode chips (LED chips) in one piece; and at least two electrodes disposed over the substrate and electrically connected to the LED chip set.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority from, and is adivisional application of, U.S. patent application Ser. No. 14/819,355filed on Aug. 5, 2015, entitled “Light-emitting diode chip package”,which claims the benefit of priority from Taiwan Patent Application No.104105987, filed on Feb. 25, 2015 and the entirety of which isincorporated by reference herein.

BACKGROUND

1. Technical Field

The disclosure relates to a chip package, and in particular to alight-emitting diode chip package.

2. Description of the Related Art

A light-emitting diode is formed by forming an active layer over asubstrate and depositing different conductive and semi-conductive layersover the substrate. The recombination radiation of electron and hole mayproduce electromagnetic radiation (such as light) through the current atthe p-n junction. For example, in the forward bias p-n junction formedby direct band gap materials such as GaAs or GaN, the recombination ofelectron and hole injected into the depletion region results inelectromagnetic radiation such as light. The aforementionedelectromagnetic radiation may lie in the visible region or thenon-visible region. Materials with different band gaps may be used toform light-emitting diodes of different colors. In addition,electromagnetic radiation in the non-visible region may be transferredto visible light through phosphorous lenses.

Since the light-emitting diode industry has recently tended towards massproduction, any increase in the yield of manufacturing light-emittingdiodes will reduce costs and result in huge economic benefits.Therefore, a simple method for manufacturing light-emitting diode chippackages that can effectively increase the yield without adding too manymanufacturing steps or too much cost is needed.

SUMMARY

The present disclosure provides a light-emitting diode chip package,including: a substrate; a light-emitting diode chip set (LED chip set)disposed over the substrate, wherein the LED chip set is formed by aplurality of light-emitting diode chips (LED chips) in one piece; and atleast two electrodes disposed over the substrate and electricallyconnected to the LED chip set.

The present disclosure also provides a light-emitting diode chippackage, including: a substrate; a light-emitting diode chip set (LEDchip set) disposed over the substrate, wherein the LED chip set isformed by wafer level chip scale packaging; and at least two electrodesdisposed over the substrate and electrically connected to the LED chipset.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIGS. 1A-1C are side views of an example light-emitting diode chippackage at various manufacturing stages in accordance with someembodiments of the present disclosure;

FIGS. 2A-2E are side views or cross-sectional views of an examplelight-emitting diode chip package at various manufacturing stages inaccordance with another embodiment of the present disclosure;

FIG. 3A is a side view of a light-emitting diode chip package inaccordance with another embodiment of the present disclosure;

FIG. 3B is a side view of a light-emitting diode chip package inaccordance with yet another embodiment of the present disclosure;

FIG. 3C is a side view of a light-emitting diode chip package inaccordance with a further embodiment of the present disclosure;

FIG. 3D is a side view of a light-emitting diode chip package inaccordance with yet a further embodiment of the present disclosure;

FIG. 4 is a side view of a light-emitting diode chip package inaccordance with another embodiment of the present disclosure; and

FIG. 5 is a side view of a light-emitting diode chip package inaccordance with another embodiment of the present disclosure.

DETAILED DESCRIPTION

The light-emitting diode chip package of the present disclosure and themethod for manufacturing this light-emitting diode chip package aredescribed in detail in the following description. In the followingdetailed description, for purposes of explanation, numerous specificdetails and embodiments are set forth in order to provide a thoroughunderstanding of the present disclosure. The specific elements andconfigurations described in the following detailed description are setforth in order to clearly describe the present disclosure. It will beapparent, however, that the exemplary embodiments set forth herein areused merely for the purpose of illustration, and the inventive conceptmay be embodied in various forms without being limited to thoseexemplary embodiments. In addition, the drawings of differentembodiments may use like and/or corresponding numerals to denote likeand/or corresponding elements in order to clearly describe the presentdisclosure. However, the use of like and/or corresponding numerals inthe drawings of different embodiments does not suggest any correlationbetween different embodiments. In addition, in this specification,expressions such as “first insulating bump disposed on/over a secondmaterial layer”, may indicate the direct contact of the first insulatingbump and the second material layer, or it may indicate a non-contactstate with one or more intermediate layers between the first insulatingbump and the second material layer. In the above situation, the firstinsulating bump may not directly contact the second material layer.

It should be noted that the elements or devices in the drawings of thepresent disclosure may be present in any form or configuration known tothose skilled in the art. In addition, the expression “a layer overlyinganother layer”, “a layer is disposed above another layer”, “a layer isdisposed on another layer” and “a layer is disposed over another layer”may indicate that the layer directly contacts the other layer, or thatthe layer does not directly contact the other layer, there being one ormore intermediate layers disposed between the layer and the other layer.

In addition, in this specification, relative expressions are used. Forexample, “lower”, “bottom”, “higher” or “top” are used to describe theposition of one element relative to another. It should be appreciatedthat if a device is flipped upside down, an element that is “lower” willbecome an element that is “higher”.

The terms “about” and “substantially” typically mean+/−20% of the statedvalue, more typically +/−10% of the stated value, more typically +/−5%of the stated value, more typically +/−3% of the stated value, moretypically +/−2% of the stated value, more typically +/−1% of the statedvalue and even more typically +/−0.5% of the stated value. The statedvalue of the present disclosure is an approximate value. When there isno specific description, the stated value includes the meaning of“about” or “substantially”.

It should be understood that, although the terms first, second, thirdetc. may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present disclosure.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this disclosure belongs. It should be appreciated that,in each case, the term, which is defined in a commonly used dictionary,should be interpreted as having a meaning that conforms to the relativeskills of the present disclosure and the background or the context ofthe present disclosure, and should not be interpreted in an idealized oroverly formal manner unless so defined.

The present disclosure utilizes a light-emitting diode chip set (LEDchip set) formed by a plurality of light-emitting diode chips (LEDchips) in one piece to simplify the manufacturing steps and reduce thecost. This LED chip set is also referred to as a wafer level chip scalepackaging LED chip set.

FIGS. 1A-1C are side views of an example light-emitting diode chippackage at various manufacturing stages in accordance with someembodiments of the present disclosure. These figures show side views ofa light-emitting diode chip package which is known to the inventor.However, the content of these figures is not well-known in the art.Therefore, these figures are merely used as references to clearlydescribe the problem to be solved in the present disclosure, and are notthe prior art of the present disclosure.

First, referring to FIG. 1A, the light-emitting diode chip package 100includes a substrate 102, a plane electrode 104 disposed over thesubstrate 102, and four independent light-emitting diode chips (LEDchips) 106. One of the electrodes of the LED chip 106 (for example thepositive electrode) is electrically connected to the plane electrode104, and another one of the electrodes of the LED chip 106 (for examplethe negative electrode) is electrically connected to the substrate 102from the bonding region 106 a by a wire 108. In addition, thelight-emitting diode chip package 100 may further include a plurality offluorescent sheets 110 disposed over each of the LED chips 106. Everyfluorescent sheet 110 has to be cut into a particular shape to exposethe underneath bonding region 106 a of the LED chips 106.

Next, referring to FIGS. 1B-1C, a shielding layer 112′ is formed overthe substrate 102. The shielding layer 112′ is used to shield the regionnot designed for light emission in the LED chips 106, namely the foursidewalls of the LED chips 106 in FIG. 1C. The shielding layer 112′exposes the top surface 110S of the fluorescent sheets 110, which isused for light emission, and exposes the portion 104 a of the planeelectrode 104, which is used to connect to the external element.

The shielding layer 112′ may be formed by the steps shown in FIGS.1B-1C. First, as shown in FIG. 1B, a shielding layer 112 is formed overthe substrate 102, plane electrodes 104, LED chips 106 and fluorescentsheets 110. It should be noted that, since the shielding layer 112 hasto exposes the top surface 110S of the fluorescent sheets 110, which isused for light emission, and the portion 104 a of the plane electrode104, which is used to connect to the external element, at the same time,the shielding layer 112 has to be formed into a particular shape by aparticular mold, so that the thickness of the shielding layer 112corresponds to the top surface 110S of the fluorescent sheets 110 andthe portion 104 a of the plane electrode 104. In other words, the regionof the shielding layer 112 corresponding to the portion 104 a of theplane electrode 104 has a thinner thickness, whereas the region of theshielding layer 112 corresponding to the top surface 110S of thefluorescent sheets 110 has a thicker thickness, as shown in FIG. 1B.

Subsequently, referring to FIG. 1C, the shielding layer 112 is etched byan etching step to exposes the top surface 110S of the fluorescentsheets 110, which is used for light emission, and the portion 104 a ofthe plane electrode 104, which is used to connect to the externalelement, at the same time. The etching step may include sand blasting orany other suitable etching method. The etched shielding layer 112 isreferred to as the shielding layer 112′.

For the light-emitting diode chip package 100, if the gap between theLED chips 106 is too great, the light spot would be resulted. Therefore,in order to prevent this light spot, the LED chips 106 in FIG. 1A haveto be closely arranged with high accuracy. For example, the gap betweentwo LED chips 106 is not greater than 100 μm. However, it cost a lot toclosely arrange the LED chips 106 with such high accuracy.

In addition, as shown in FIG. 1A, every fluorescent sheet 110 disposedover the LED chips 106 has to be cut into a particular shape to exposethe underneath bonding region 106 a of the LED chips 106. However, italso costs a lot to cut every fluorescent sheets 110 disposed over theLED chips 106 into particular shapes. In addition, since every LED chip106 requires one wire 108 to electrically connect the substrate 102, theplurality of wires 108 occupy a large area in the substrate 102, whichin turn decreases the usable area of the substrate 102.

Furthermore, since the shielding layer 112 in FIGS. 1B-1C has to beformed into a particular shape by a particular mold, it also costs a lotto form this shielding layer 112.

Therefore, in order to solve the abovementioned problem, anotherlight-emitting diode chip package is provided in another embodiment ofthe present disclosure. This light-emitting diode chip package may beformed by simplified manufacturing steps, which in turn reduces thecost.

FIGS. 2A-2D are side views or cross-sectional views of an examplelight-emitting diode chip package at various manufacturing stages inaccordance with another embodiment of the present disclosure.

First, referring to FIG. 2A, the light-emitting diode chip package 200includes a substrate 202, a light-emitting diode chip set 214 (LED chipset 214) disposed over the substrate 202, and at least two electrodes204A and 204B disposed over the substrate 202 and electrically connectedto the LED chip set 214. The substrate 202 may include, but is notlimited to, a ceramic substrate, a copper substrate, an aluminumsubstrate, or any other suitable heat-releasing substrate.

The LED chip set 214 is formed by a plurality of light-emitting diodechips 206A, 206B, 206C and 206D (LED chips 206A, 206B, 206C and 206D) inone piece. Alternately, this LED chip set 214 is also referred to as awafer level chip scale packaging LED chip set 214. The plurality oflight-emitting diode chips 206A, 206B, 206C and 206D may independentlyinclude, but are not limited to, an ultraviolet LED chip, a blue LEDchip, a green LED chip, a red LED chip, or any other suitable LED chip.

The wafer level chip scale packaging LED chip set 214 formed by theplurality of LED chips 206A, 206B, 206C and 206D is different from theindependent light-emitting diode chips formed by conventional chippackaging technology. In particular, the conventional chip packagingtechnology would perform a cutting step first to separate each of theLED chips formed over the wafer, and then each of the independent LEDchips is packaged. Unlike the conventional chip packaging technology,the LED chip set 214 formed by the plurality of LED chips 206A, 206B,206C and 206D (also referred to as the wafer level chip scale packagingLED chip set 214) is packaged at the wafer level. For example, theplurality of the LED chips in the wafer level chip scale packaging LEDchip set 214 are electrically connected to each other in the waferlevel. Subsequently, a cutting step is performed to singulate the LEDchip set 214 formed by the plurality of LED chips 206A, 206B, 206C and206D. The semiconductor substrate between the plurality of LED chips206A, 206B, 206C and 206D, which is used to connect this plurality ofLED chips 206A, 206B, 206C and 206D, is not cut.

In particular, FIG. 2B is a cross-sectional view along line 2B-2B inFIG. 2A in accordance with some embodiments of the present disclosure.In addition, the electrodes 204, pillar portion 220, conductive via 222and wire 208 which are not disposed on the line 2B-2B are also shown inFIG. 2B in order to clearly describe the present disclosure.

Using the wafer level chip scale packaging LED chip set 214, which isformed by four light-emitting diode chips 206A, 206B, 206C and 206D inone piece, in FIG. 2B as an example, the four LED chips 206A, 206B, 206Cand 206D are electrically connected to each other by the conductive wirestructure in the semiconductor substrate 216 of the wafer at the waferdesign and wafer manufacture stages. The conductive wire structure 218may include, but is not limited to, an interconnection structure in thesemiconductor substrate 216. Subsequently, a cutting step is performedto singulate the LED chip set 214 formed by these four LED chips 206A,206B, 206C and 206D. The semiconductor substrate 216 between theplurality of LED chips 206A, 206B, 206C and 206D, which is used toconnect this plurality of LED chips 206A, 206B, 206C and 206D, is notcut.

In other words, the LED chip set 214 includes the semiconductorsubstrate 216, and the plurality of LED chips 206A, 206B, 206C and 206Dare disposed in the semiconductor substrate 216 and are electricallyconnected to each other by a wire structure 218 in the semiconductorsubstrate 216. For example, in one embodiment as shown in FIG. 2A-2B,one of the electrodes 204 may be electrically connected to the positiveelectrode of the LED chip 206A through the bonding region 214 a of theLED chip set 214 by the wire 208. Then, the negative electrode of theLED chip 206A may be electrically connected to the positive electrode ofthe LED chip 206B by the wire structure 218A. Subsequently, the negativeelectrode of the LED chip 206B may be electrically connected to thepositive electrode of the LED chip 206C by the wire structure 218B. Thenegative electrode of the LED chip 206C may be electrically connected tothe positive electrode of the LED chip 206D by the wire structure 218C.Finally, the negative electrode of the LED chip 206D may be electricallyconnected to another electrode 204 through the bonding region 214 a andanother wire 208.

The semiconductor substrate 216 may include, but is not limited to, asilicon substrate. In addition, the semiconductor substrate 216 mayinclude an element semiconductor which may include germanium; a compoundsemiconductor which may include silicon carbide, gallium arsenide,gallium phosphide, indium phosphide, indium arsenide and/or indiumantimonide; an alloy semiconductor which may include SiGe alloy, GaAsPalloy, AlInAs alloy, AlGaAs alloy, GaInAs alloy, GaInP alloy and/orGaInAsP alloy; or a combination thereof. In addition, the semiconductorsubstrate 216 may include a semiconductor-on-insulator.

As shown in FIG. 2A-2B, the plurality of light-emitting diode chips206A, 206B, 206C and 206D in the LED chip set 214 has already beenclosely arranged with high accuracy. For example, the gap between twoLED chips 206 is not greater than 100 μm. Therefore, the manufacturingstep for the light-emitting diode chip package 200 need not closelyarrange the LED chips, which are separated from each other, with highaccuracy as shown in FIG. 1A, and the cost may be greatly reduced. Inaddition, the light spot issue may be prevented by closely arranging theplurality of light-emitting diode chips 206A, 206B, 206C and 206D.

In addition, in one embodiment as shown in FIG. 2A-2B, the plurality ofLED chips 206A, 206B, 206C and 206D of the light-emitting diode chippackage 200 is juxtaposed or placed side by side.

Still referring to FIG. 2A-2B, the light-emitting diode chip package 200may further include at least one pillar portion 220 disposed over thesubstrate 202. In addition, at least one of the electrodes 204 isdisposed over the pillar portion 220. For example, in the embodimentshown in FIG. 2A, the light-emitting diode chip package 200 includes twopillar portions 220A and 220B disposed over the substrate 202, and thetwo pillar portions 220A and 220B are disposed at two corner regions202C of the substrate 202. In addition, the two electrodes 204A and 204Bare disposed over the top surfaces of these two pillar portions 220A and220B respectively. The two electrodes 204A and 204B may be electricallyconnected to the bonding region 214 a of the LED chip set 214 by thewire 208.

In addition, each of the pillar portions 220A and 220B includes aconductive via 222, and the conductive via 222 electrically connects theelectrode 204 and the substrate 202. In particular, the conductive via222 is a through hole of the pillar portion 220. This through holepenetrates through the top surface and bottom surface of the pillarportion 220. A conductive material is filled in the conductive via 222.Therefore, the electrodes 204 disposed over the top surface of thepillar portion 220 may be electrically connected to the substrate 202under the pillar portion 220 by the conductive via 222.

It should be noted that the exemplary embodiment set forth in FIGS.2A-2B is merely for the purpose of illustration. In addition to theembodiment set forth in FIGS. 2A-2B, the light-emitting diode chippackage may include other amount of pillar portions. This will bedescribed in detail in the following description. Therefore, theinventive concept and scope are not limited to the exemplary embodimentshown in FIGS. 2A-2B.

The material of the pillar portion 220 may include, but is not limitedto, ceramics, glass, epoxy resin, metal, or any other suitable material.The material of the electrodes 204A and 204B may include, but is notlimited to, a single layer or multiple layers of copper, aluminum,tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium,an alloy thereof, a combination thereof, or any other metal materialwith good conductivity. The electrodes 204A and 204B may be formed overthe top surface of the pillar portion 220 by electroplating, sputtering,resistive thermal evaporation, electron beam evaporation or any othersuitable deposition processes.

In addition, the conductive via 222 of the pillar portion 220 may beformed in the pillar portion 220 by laser cutting, lithography andetching, wheel cutting, mechanical drilling, or a combination thereof,or any other suitable method. The etching step may include sandblasting, reactive ion etching (RIE), plasma etching, or any othersuitable etching method. The conductive material disposed in theconductive via 222 may include, but is not limited to, copper, aluminum,tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium,an alloy thereof, a combination thereof, or any other metal materialwith good conductivity. In one embodiment, the conductive materialdisposed in the conductive via 222 is the same as the material of theelectrodes 204A and 204B, and the conductive material and the electrodes204A and 204B may be formed in the same metal deposition process.However, in other embodiments, the conductive material disposed in theconductive via 222 may be formed in a metal deposition process otherthan that for forming the electrodes 204A and 204B, and the conductivematerial may be different from the material of the electrodes 204A and204B.

Next, FIG. 2D is a cross-sectional view of the light-emitting diode chippackage 200 along line 2D-2D in FIG. 2C in accordance with someembodiments of the present disclosure. In addition, the electrodes 204,pillar portion 220, conductive via 222 and wire 208 which are notdisposed on the line 2D-2D is also shown in FIG. 2D in order to clearlydescribe the present disclosure. As shown in FIGS. 2C-2D, thelight-emitting diode chip package 200 may further include a fluorescentsheet 210 disposed over the LED chip set 214.

In some embodiments of the present disclosure, the fluorescent sheet 210may include, but is not limited to, a fluorescent powder-blended ceramicsheet (referred to as a ceramic fluorescent sheet). The ceramicfluorescent sheet may be formed by sintering the fluorescent powder andthe ceramic powder at high temperature. The examples of ceramic powdersinclude silicon oxide, aluminum oxide or any other suitable materials.The examples of fluorescent powders include yttrium aluminium garnet(Y₃Al₅O₁₂, YAG), lutetium aluminium garnet (Lu₃Al₅O₁₂, LuAG), silicate,nitride or any other suitable fluorescent powder. The fluorescentpowders may convert the light emitted by the light-emitting diode chipinto white light. In other embodiments, the fluorescent sheet 210 mayinclude, but is not limited to, a glass sheet or a silica gel blendedwith the fluorescent powder.

As shown in FIGS. 2C-2D, the fluorescent sheet 210 only need to exposethe bonding region 214 a of the LED chip set 214 at the right side.Therefore, the fluorescent sheet 210 need not be cut into a particularshape to expose every LED chip as shown in FIG. 1A. Therefore, byutilizing the LED chip set 214 of the present disclosure, thecomplicated cutting process may be simplified, such that themanufacturing steps may be simplified and the cost may be reduced.

In addition, the plurality of light-emitting diode chips 206A, 206B,206C and 206D need only one wire 208 to electrically connect theelectrode 204 through the bonding region 214 a of the LED chip set 214.Therefore, compared to the embodiment shown in FIG. 1A, in which each ofthe LED chips needs one wire, the LED chip set 214 of the presentdisclosure may greatly reduce the amount of wire 208. Therefore, thearea of the substrate 202 occupied by the wire may be greatly reduced,which in turn increases the usable area of the substrate 102.

Referring to FIGS. 2D-2E, in one embodiment as shown in FIG. 2D, theheight difference H between the top surface 204S of the electrode 204disposed over the pillar portion 220 and the top surface 210S of thefluorescent sheet 210 may range from about 0 μm to about 50 μm, forexample from about 10 μm to about 40 μm. In one embodiment, the heightdifference H between the top surface 204S of the electrode 204 and thetop surface 210S of the fluorescent sheet 210 may be 0. In other words,the height of the top surface 204S of the electrode 204 disposed overthe pillar portion 220 is equal to that of the top surface 210S of thefluorescent sheet 210.

Next, in the step shown in FIG. 2E, a shielding layer 212 is formed overthe substrate 202. The shielding layer 212 is used to shield the regionnot designed for light emission in the LED chip set 214, namely thesidewall of the LED chip set 214 in FIG. 2E. The shielding layer 212exposes the top surface 210S of the fluorescent sheets 210, which isused for light emission, and exposes the top surface 204S of theelectrode 204, which is used to connect to the external element.

Since the height difference H between the top surface 204S of theelectrode 204 and the top surface 210S of the fluorescent sheet 210 inthe light-emitting diode chip package 200 is very small (about 0 μm toabout 50 μm), the shielding layer 212 need not be formed into aparticular shape by a particular mold as shown in FIGS. 1B-1C.Therefore, by disposing the top surface 204S of the electrode 204 at thesame horizontal level as the top surface 210S of the fluorescent sheet210, namely the height difference is about 0 μm to about 50 μm, the stepin which the shielding layer is formed into a particular shape by aparticular mold is no longer needed. Therefore, the manufacturing stepsmay be simplified and the cost may be reduced.

It should be noted that the exemplary embodiment set forth in FIGS.2A-2E is merely for the purpose of illustration. In addition to theembodiment set forth in FIGS. 2A-2E in which the light-emitting diodechip package includes two pillar portions, the light-emitting diode chippackage may include another amount of pillar portions, as shown in theembodiment in FIGS. 3A-3B. This will be described in detail in thefollowing description. Therefore, the inventive concept and scope arenot limited to the exemplary embodiment shown in FIGS. 2A-2E.

FIG. 3A is a side view of a light-emitting diode chip package inaccordance with another embodiment of the present disclosure. Thedifference between the embodiments shown in FIGS. 3A and 2A-2E is thatthe light-emitting diode chip package 310 includes three pillar portions220A, 220B and 220C disposed at three corner regions 202C of thesubstrate 202. Since the amount of pillar portions 220 that may be usedto electrically connect to the external element increases, thelight-emitting diode chip package 310 shown in FIG. 3A may improve thedevice-design flexibility. It should be noted that the shielding layeris not shown in FIG. 3A and the following figures are presented in orderto clearly describe the present disclosure.

FIG. 3B is a side view of a light-emitting diode chip package inaccordance with another embodiment of the present disclosure. Thedifference between the embodiments shown in FIGS. 3B and 3A is that thelight-emitting diode chip package 320 includes four pillar portions220A, 220B, 220C and 220D disposed at four corner regions 202C of thesubstrate 202. Since the amount of pillar portions 220 that may be usedto electrically connect to the external element increases, thelight-emitting diode chip package 320 shown in FIG. 3B may improve thedevice-design flexibility.

It should be noted that the exemplary embodiments set forth in FIGS.2A-3B is merely for the purpose of illustration. In addition to theembodiments set forth in FIGS. 2A-3B, the electrode of the embodimentsof the present disclosure may be electrically connected to the substrateby other methods, as shown in the embodiment in FIG. 3C. This will bedescribed in detail in the following description. Therefore, theinventive concept and scope are not limited to the exemplary embodimentsshown in FIGS. 2A-3B.

FIG. 3C is a side view of a light-emitting diode chip package inaccordance with another embodiment of the present disclosure. Thedifference between the embodiments shown in FIGS. 3C and 2A-3B is thatthe electrode 204 of the light-emitting diode chip package 330 isdisposed over the top surface and the sidewall of the pillar portion220, and the electrode 204 is electrically connected to the substrate202 through the portion of the electrode 204 disposed over the sidewallof the pillar portion 220. The pillar portion 220 does not include anyconductive via. Therefore, the step for forming the conductive via maybe eliminated and the cost may be further reduced.

It should be noted that the exemplary embodiments set forth in FIGS.2A-3C are merely for the purpose of illustration. In addition to theembodiments set forth in FIGS. 2A-3C which include the pillar portion,the present disclosure may include a protrusion portion with othershapes, as shown in the embodiment in FIG. 3D. This will be described indetail in the following description. Therefore, the inventive conceptand scope are not limited to the exemplary embodiments shown in FIGS.2A-3C.

FIG. 3D is a side view of a light-emitting diode chip package inaccordance with another embodiment of the present disclosure. Thedifference between the embodiments shown in FIGS. 3D and 2A-3C is thatthe light-emitting diode chip package 340 includes a rectangular portion350 disposed over the substrate 202, and the electrodes 204A and 204Bare disposed over the rectangular portion 350. By utilizing therectangular portion 350, the structure reliability may be furtherimproved.

In addition, the light-emitting diode chip package 340 may furtherinclude a fluorescent sheet 210 disposed over the LED chip set 214. Theheight difference between the top surface of the electrode 204 disposedover the rectangular portion 350 and the top surface of the fluorescentsheet 210 may range from about 0 μm to about 50 μm, for example fromabout 10 μm to about 40 μm. In one embodiment, the height difference Hbetween the top surface 204S of the electrode 204 and the top surface210S of the fluorescent sheet 210 may be 0. In other words, the heightof the top surface 204S of the electrode 204 disposed over therectangular portion 350 is equal to that of the top surface 210S of thefluorescent sheet 210.

It should be noted that the exemplary embodiments set forth in FIGS.2A-3D are merely for the purpose of illustration. In addition to theembodiments set forth in FIGS. 2A-3D which include only one fluorescentsheet, the present disclosure may include a plurality of fluorescentsheets, as shown in the embodiment in FIG. 4. This will be described indetail in the following description. Therefore, the inventive conceptand scope are not limited to the exemplary embodiments shown in FIGS.2A-3D.

FIG. 4 is a side view of a light-emitting diode chip package inaccordance with another embodiment of the present disclosure. Thedifference between the embodiments shown in FIGS. 4 and 2A-3D is thatthe light-emitting diode chip package 400 includes a plurality offluorescent sheets 410A, 410B, 410C and 410D disposed over the LED chipset 214. Each of the fluorescent sheets 410 is disposed corresponding tothe plurality of underneath light-emitting diode chips 206A, 206B, 206Cand 206D, respectively.

It should be noted that the exemplary embodiments set forth in FIGS.2A-4 are merely for the purpose of illustration. In addition to theembodiments set forth in FIGS. 2A-4 in which the LED chip set iselectrically connected to the electrode by a solid wire, the LED chipset may be electrically connected to the electrode by a conductive layerdisposed in or disposed over the substrate.

FIG. 5 is a side view of a light-emitting diode chip package inaccordance with another embodiment of the present disclosure. As shownin FIG. 5, the LED chip set 214 is electrically connected to theelectrode 204A through the conductive via 222 by a conductive layer 500disposed over the substrate 202, and the LED chip set 214 iselectrically connected to the electrode 204B through the conductive via222 by another conductive layer 502 disposed over the substrate 202. Inthis embodiment, the LED chip set 214 is not electrically connected tothe electrodes 204A and 204B by any solid wire, for example the wire 208described previously. In addition, although FIG. 5 only shows that theconductive layers 500 and 502 are disposed over the substrate 202, thoseskilled in the art will appreciate that the conductive layers 500 and502 may also be disposed in the substrate 202 and may be electricallyconnected to the LED chip set 214 by a conductive via. The conductivelayers 500 and 502 may include, but are not limited to, metal or anyother suitable conductive material.

In addition, although the aforementioned embodiments all utilize wiresto electrically connect the LED chip set and the electrode, thoseskilled in the art will appreciate that the LED chip set may beelectrically connected to the underneath substrate by a flip-chiparrangement. And the LED chip set may be further electrically connectedto the electrode through the interconnection structure in the substrateand the conductive via in the pillar portion. Therefore, the inventiveconcept and scope are not limited to the exemplary embodiments whichutilize the wires.

In summary, by utilizing the light-emitting diode chip set formed by aplurality of LED chips in one piece (namely the wafer level chip scalepackaging LED chip set), the manufacturing step for the light-emittingdiode chip package need not closely arrange the LED chips which areseparated from each other with high accuracy. Therefore, the cost may begreatly reduced. In addition, the area of the substrate occupied by thewire may be greatly reduced, which in turn increases the usable area ofthe substrate. Furthermore, the fluorescent sheet does not need to becut by complicated cutting processes. Therefore, the manufacturing stepsmay be simplified further and the cost may be reduced further. And bydisposing the top surface of the electrode at the same horizontal levelas the top surface of the fluorescent sheet, the step in which theshielding layer is formed into a particular shape by a particular moldis no longer needed. Therefore, the manufacturing steps may besimplified further and the cost may be reduced further.

Although some embodiments of the present disclosure and their advantageshave been described in detail, it should be understood that variouschanges, substitutions and alterations can be made herein withoutdeparting from the spirit and scope of the disclosure as defined by theappended claims. For example, it will be readily understood by thoseskilled in the art that many of the features, functions, processes, andmaterials described herein may be varied while remaining within thescope of the present disclosure. Moreover, the scope of the presentapplication is not intended to be limited to the particular embodimentsof the process, machine, manufacture, composition of matter, means,methods and steps described in the specification. As one of ordinaryskill in the art will readily appreciate from the disclosure of thepresent disclosure, processes, machines, manufacture, compositions ofmatter, means, methods, or steps, presently existing or later to bedeveloped, that perform substantially the same function or achievesubstantially the same result as the corresponding embodiments describedherein may be utilized according to the present disclosure. Accordingly,the appended claims are intended to include within their scope suchprocesses, machines, manufacture, compositions of matter, means,methods, or steps.

What is claimed is:
 1. A light-emitting diode chip package, comprising:a substrate; a plurality of light-emitting diode chips (LED chips)disposed over the substrate; a plane electrode disposed over thesubstrate and electrically connected to one of the plurality oflight-emitting diode chips; and a wire electrically connected one of theplurality of light-emitting diode chips to the substrate.
 2. Thelight-emitting diode chip package as claimed in claim 1, furthercomprising: a plurality of fluorescent sheets disposed over each of theLED chips.
 3. The light-emitting diode chip package as claimed in claim2, wherein the fluorescent sheet has a particular shape exposing abonding region of the LED chip.
 4. The light-emitting diode chip packageas claimed in claim 3, wherein the wire is bonded to the bonding regionof the LED chip.
 5. The light-emitting diode chip package as claimed inclaim 1, wherein the plurality of light-emitting diode chips areindependent from each other.
 6. The light-emitting diode chip package asclaimed in claim 2, further comprising: a shielding layer disposed overthe substrate.
 7. The light-emitting diode chip package as claimed inclaim 6, wherein the shielding layer shields four sidewalls of the LEDchips.
 8. The light-emitting diode chip package as claimed in claim 6,wherein the shielding layer exposes a top surface of the fluorescentsheet.
 9. The light-emitting diode chip package as claimed in claim 6,wherein the shielding layer exposes a portion of the plane electrode.10. The light-emitting diode chip package as claimed in claim 1, whereinthe plurality of LED chips is juxtaposed.
 11. The light-emitting diodechip package as claimed in claim 1, wherein the wire is a solid wire,and one of the plurality of light-emitting diode chips is electricallyconnected to the substrate by the solid wire.
 12. The light-emittingdiode chip package as claimed in claim 1, wherein the wire is aconductive layer, and one of the plurality of light-emitting diode chipsis electrically connected to the substrate by the conductive layer.